Abstract
This manuscript studies why the same LLM can produce different outputs on different TPU generations and what is required for those outputs to agree. Probing TPU v4, v5e, and v6e from outside, it localizes cross-generation bf16 matrix-multiplication differences to the compiled cross-pass reduction order and reproduces them with a CPU emulator. Matching matrix multiplications alone does not make the model agree; whole-program pinning yields identical logits and greedy text across all three generations, and identical vLLM output on v5e and v6e. The public record is intentionally limited while the manuscript is under review.
Public record
This page records a manuscript under double-blind review at MLSys 2027 without implying acceptance. A public PDF, complete citation metadata, code, and artifacts will be added only when they are legitimately available.